This invention relates to a bus protocol which arbitrates and provides access to a system bus which is shared by a number of modules in a computing system. In particular, the invention relates to the protocol and the apparatus for implementing the bus protocol.
It is a common practice in computing systems in which there are a number of modules sharing a system bus to provide each module on the bus with a different priority. In some systems the priority of each module is fixed and in others a token passing system is provided in which priority is passed from one module to the next. In either of these systems of arbitrating use of the bus, a module having the highest priority may monopolize use of the bus line to the detriment of the lower priority modules. Such monopolization of the bus occurs regardless of the importance of the particular instructions being executed by the module having the highest priority on the bus. The performance of such systems may suffer when important instructions in modules having a low priority have to wait in order to be performed.
A system bus has lines for carrying addresses, commands, data and control signals between modules. Instructions are often delivered in a phase for the sending of an address with its command and a phase for the sending of data. Therefore, the data bus may be used in a separate operation at the same time that a new command is being sent out on the system address bus. Prior art systems often deligate the task of determining the beginning and end of a data phase or instruction phase to a single module in the computing system. This may tend to be a burden which slows the system as control signals are transferred back and forth to the assigned bus control module. It is an object of the present invention to distribute the control of bus access. It is a further object of the present invention to increase the ability of a system to take advantage of overlap between the system address and system data buses.